Archive for the PLI Category

Note: ModelSim 的 PLI Example “traverse_design”

Posted in HDL, PLI, Verilog on 2011 年 05 月 16 日 by Kun-Yi

這個Example除了把 Modelsim 安裝好後, 還要看環境安裝對應的 compiler,  因為在XP 32bits上測試, 所以需要 “gcc-4.2.1-mingw32vc9”的package 解壓縮後(看 traverse_design.do會有一些提示), 放在安裝目錄即可. 另外 traverse_design.do 最後會直接離開Modelsim 需要comment最後指令

下面是執行過程, 主要是dump  pin/wire 的information.

do traverse_design.do
# Model Technology ModelSim SE vlog 10.0a Compiler 2011.02 Feb 20 2011
# — Compiling UDP multiplexer
# — Compiling UDP sudp
# — Compiling module dff
# — Compiling module top
#
# Top level modules:
#     top
# gcc -g -c -m32 -Wall -ansi -pedantic -I. -IC:/modeltech_10.0a/include  pli_test.c
# gcc -shared -lm -m32 -Wl,-Bsymbolic -Wl,-export-dynamic -o  pli_test.dll pli_test.o  -LC:/modeltech_10.0a/win32 -lmtipli
# vsim -c -pli ./pli_test.dll top
# ** Note: (vsim-3812) Design is being optimized…
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# Loading ./pli_test.dll
# Loading work.top(fast)
# Loading work.dff(fast)
#
# ===========================
# Results of Design Traversal
# ===========================
#
# Module name is top.
#   Type           is accModule (20).
#   Full Type      is accTopModule (224).
#   Cell Instance  is FALSE.
#   Def Name       is top.
#   Delay Mode     is 0 (accDelayModeNone).
#   File           is top.v.
#   Line No        is 0.
#   Full Name      is top.
#   Time Precision is -9 (1 ns).
#   Time Unit      is -9 (1 ns).
#   Top Module     is TRUE.
#
#   Port name is ain.
#     Type          is accPort (35).
#     Full Type     is accVectorPort (256).
#     Direction     is accInout.
#     Port Index    is 0.
#     Line No       is 14.
#     File          is top.v.
#     Port Size     is Vector of 4 bits.
#     Parent        is top of type accTopModule.
#
#   Port Bit #1: ———-
#
#   Port name is ain[3].
#     Type          is accPortBit (214).
#     Full Type     is accPortBit (214).
#     Direction     is accInout.
#     Line No       is 14.
#     File          is top.v.
#     Port Size     is Scalar.
#     Parent        is top of type accTopModule.

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