Archive for the HDL Category

Note: Modelsim Examples 下的 “sc_vlog”

Posted in HDL, SystemC, Verilog on 2011 年 05 月 16 日 by Kun-Yi

它是一個透過 SystemC  ringbuf.h 去執行 Verilog module 的範例

ringbuf.h 內是宣告繼承所謂的 sc_foreign_module 來執行外部module, 這里是 ringbuf.v

在 run.do 可以看到先將所有 verilog 都compile 然後做 scgenmod -bool ringbuf > ringbuf.h 手動產生 foregin  module 的連結, 這裡的 ringbuf > ringbuf.h 是將 ringbuf 當成參數傳進 ringbuf.h, 這各參數這裡是當成 ringbuf.v 內的 hdl_name 接收, 然後compile test_ringbuf 之後, 去跑 simulation.

算是一個用SystemC寫Test bench 的範例

Note: Modelsim 的SystemC 的Example, “sc_basic”gold

Posted in HDL, SystemC on 2011 年 05 月 16 日 by Kun-Yi

底下就是依序的指令(省略進入目錄的過程), 與執行結果, SystemC 目前主要用來驗證演算法的執行是否正確, 是C語言的語法 加入HW的元素, 有多Task可以代表硬體的平行執行.

vlib work
sccom -g basic.cpp
#
# Model Technology ModelSim SE sccom 10.0a compiler 2011.02 Feb 20 2011
#
# Exported modules:
#     top
sccom -link
#
# Model Technology ModelSim SE sccom 10.0a compiler 2011.02 Feb 20 2011
vsim -voptargs=+acc work.top
# vsim -voptargs=+acc work.top
# ** Note: (vsim-3812) Design is being optimized…
# Loading C:\modeltech_10.0a\examples\systemc\sc_basic\gold\work\_sc\win32_gcc-4.2.1\systemc.so
# Loading C:\modeltech_10.0a\examples\systemc\sc_basic\gold\work.top
run
# 1 main_action_method called
# 1 main_action_thread called
# 3 main_action_cthread called

Note: ModelSim 的 PLI Example “traverse_design”

Posted in HDL, PLI, Verilog on 2011 年 05 月 16 日 by Kun-Yi

這個Example除了把 Modelsim 安裝好後, 還要看環境安裝對應的 compiler,  因為在XP 32bits上測試, 所以需要 “gcc-4.2.1-mingw32vc9”的package 解壓縮後(看 traverse_design.do會有一些提示), 放在安裝目錄即可. 另外 traverse_design.do 最後會直接離開Modelsim 需要comment最後指令

下面是執行過程, 主要是dump  pin/wire 的information.

do traverse_design.do
# Model Technology ModelSim SE vlog 10.0a Compiler 2011.02 Feb 20 2011
# — Compiling UDP multiplexer
# — Compiling UDP sudp
# — Compiling module dff
# — Compiling module top
#
# Top level modules:
#     top
# gcc -g -c -m32 -Wall -ansi -pedantic -I. -IC:/modeltech_10.0a/include  pli_test.c
# gcc -shared -lm -m32 -Wl,-Bsymbolic -Wl,-export-dynamic -o  pli_test.dll pli_test.o  -LC:/modeltech_10.0a/win32 -lmtipli
# vsim -c -pli ./pli_test.dll top
# ** Note: (vsim-3812) Design is being optimized…
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# Loading ./pli_test.dll
# Loading work.top(fast)
# Loading work.dff(fast)
#
# ===========================
# Results of Design Traversal
# ===========================
#
# Module name is top.
#   Type           is accModule (20).
#   Full Type      is accTopModule (224).
#   Cell Instance  is FALSE.
#   Def Name       is top.
#   Delay Mode     is 0 (accDelayModeNone).
#   File           is top.v.
#   Line No        is 0.
#   Full Name      is top.
#   Time Precision is -9 (1 ns).
#   Time Unit      is -9 (1 ns).
#   Top Module     is TRUE.
#
#   Port name is ain.
#     Type          is accPort (35).
#     Full Type     is accVectorPort (256).
#     Direction     is accInout.
#     Port Index    is 0.
#     Line No       is 14.
#     File          is top.v.
#     Port Size     is Vector of 4 bits.
#     Parent        is top of type accTopModule.
#
#   Port Bit #1: ———-
#
#   Port name is ain[3].
#     Type          is accPortBit (214).
#     Full Type     is accPortBit (214).
#     Direction     is accInout.
#     Line No       is 14.
#     File          is top.v.
#     Port Size     is Scalar.
#     Parent        is top of type accTopModule.

Note : PPM (Power Plane Management) CPLD for Atom + SCH

Posted in HDL on 2008 年 11 月 14 日 by Kun-Yi

目前只做到 S4/S5 to S0 的 Function simulation, source clock 也不是用實際的32.768KHz,  先用簡單的用 32KHz替代, 結果與程式碼如下, 基本上從 Intel 的 Altera 的 AHDL 手工轉成 Verilog

image

/*
 * PPM(Power Plane Management for XXX Project)
 * Function description :
 *      Power Sequence control
 *      ref. Power Plane Management and LPC to SPI bridging Solution, Intel 391878.pdf
 *
 * Create by : Kun-Yi Chen
 * Data : Nov. 12 2008
 * Language : Verilog, RTL
 * Revesion : 0.1
 */

module PPM
(
    // ------------------------------------------------------------------------
    // inputs
    SMC_ONOFF_N,        // System Managment controller On/Off, 
                        // debounced copy of the power button.
    PM_RSMRST_PWRGD,    // Resume Reset Power Good
    SUS_CLK,            // Suspend Clock, 32.7680Khz
    PM_ALL_SYS_PWRGD,   // All System Power Good
    PM_IMVP_PWRGD,      // IMVP Power Good, Power for CPU is stable
    PM_SYSRST_N,        // System Reset button,
                        // debounced copy of the reset button
    SMC_RST_N,          // Indicates the 3.3v standby power is stable
    //
    // SCH to CPLD
    SLPMODE,            // Sleep mode, if (SLPMODE) enterd S3 else enterd S4/S5
    SLPRDY_N,           // Sleep Ready
    RSTRDY,             // Reset Ready
    // ------------------------------------------------------------------------
    // outputs
    PM_SLP_S4_N,        // Sleep S4
    PM_SCH_RSMRST_N,    // Resume Well Reset
    PM_SLP_S3_N,        // Sleep S3
    IMVP_VR_ON,         // IMVP Voltage Regulator On
    SCH_PWROK,          // Power OK, SCH core power is stable
    PM_RSTWARN,         // Reset Warning
    RST_N,              // System Reset
    //
    EC_A20M_N,          // EC A20 match
    EC_INIT_N           // EC initial
);
// port declare
input SMC_ONOFF_N;
input PM_RSMRST_PWRGD;
input SUS_CLK;
input PM_ALL_SYS_PWRGD;
input PM_IMVP_PWRGD;
input SLPMODE;
input SLPRDY_N;
input RSTRDY;
input PM_SYSRST_N;
input SMC_RST_N;

output PM_SLP_S4_N;
output PM_SCH_RSMRST_N;
output PM_SLP_S3_N;
output IMVP_VR_ON;
output SCH_PWROK;
output PM_RSTWARN;
output RST_N;
//
// single declare
//
reg PM_SLP_S4_N;
reg PM_SCH_RSMRST_N;
reg PM_SLP_S3_N;
reg IMVP_VR_ON;
reg SCH_PWROK;
reg PM_RSTWARN;
reg RST_N;

input EC_A20M_N;
input EC_INIT_N;
    
reg [7:0] CNT8B;
reg [11:0] CNT12B;

reg RST_CNT8B_N;
reg RST_CNT12B_N;

parameter [3:0] 
    S4 = 0,
    S3toS0_sec1 = 1, S3toS0_sec2 = 2, S3toS0_sec3 = 3,
    S3toS0_clr1 = 4, S3toS0_clr2 = 5,
    S0 = 6, S0toS3 =7, S3 = 8,
    warmreset = 9;

`define DEL 1


reg [3:0] ST_PM; // power managment state machine

always @( posedge SUS_CLK or negedge SMC_RST_N )
begin
    if (~SMC_RST_N) begin // asynchronous reset
        ST_PM <= #`DEL S4;
    end
    else begin
      case (ST_PM)
        S4: begin
            //PM_RSMRST_PWRGD <= #`DEL 1'b0;
            PM_SLP_S3_N <= #`DEL 0;
            
            IMVP_VR_ON <= #`DEL 0;
            SCH_PWROK <= #`DEL 0;
            PM_RSTWARN <= #`DEL 1;
            RST_N <= #`DEL 0;

            RST_CNT8B_N <= #`DEL 0;
            RST_CNT12B_N <= #`DEL 0;
            //CNT8B <= #`DEL 8'b0;
            //CNT12B <= #`DEL 12'b0;

            if (~SMC_ONOFF_N) begin 
              // when Power Button is press
              PM_SLP_S4_N <= #`DEL 1;
              if (PM_RSMRST_PWRGD) begin
                PM_SCH_RSMRST_N <= #`DEL 1;
                ST_PM <= #`DEL S3toS0_sec1;
              end
            end
            else begin
              PM_SLP_S4_N <= #`DEL 0;
            end
        end

        S3toS0_sec1: begin
            PM_SLP_S4_N <= #`DEL 1;
            PM_SCH_RSMRST_N <= #`DEL 1;
            PM_RSTWARN <= #`DEL 1;

            RST_CNT12B_N <= #`DEL 1;
            //CNT12B <= #`DEL CNT12B + 1;

            if (PM_SCH_RSMRST_N & (CNT12B >= 1300)) begin // wait 40ms(1300 * 1/32.768KHz)
                PM_SLP_S3_N <= #`DEL 1;
            end
            else begin
                PM_SLP_S3_N <= #`DEL 0;
            end

            if (PM_ALL_SYS_PWRGD) begin // wait for SCH Power to become stable
                ST_PM <= #`DEL S3toS0_clr1;
            end
        end

        S3toS0_clr1: begin // the purpose of this state is the clear the counter
            RST_CNT12B_N <= #`DEL 0;
            RST_CNT8B_N <= #`DEL 0;
            //CNT12B <= #`DEL 12'b0;
            //CNT8B <= #`DEL 8'b0;

            PM_SLP_S4_N <= #`DEL 1;
            PM_SCH_RSMRST_N <= #`DEL 1;
            PM_SLP_S3_N <= #`DEL 1;
            PM_RSTWARN <= #`DEL 1;
            ST_PM <= #`DEL S3toS0_sec2;
        end

        S3toS0_sec2: begin
            PM_SLP_S4_N <= #`DEL 1;
            PM_SCH_RSMRST_N <= #`DEL 1;
            PM_SLP_S3_N <= #`DEL 1;
            PM_RSTWARN <= #`DEL 1;

            if (CNT8B >= 104) begin
                IMVP_VR_ON <= #`DEL 1;
            end
            else begin
                RST_CNT8B_N <= #`DEL 1;
                //CNT8B <= #`DEL CNT8B + 1;
            end

            if (PM_IMVP_PWRGD) begin
                RST_CNT12B_N <= #`DEL 1;
                //CNT12B <= #`DEL CNT12B + 1;
            end

            if (CNT12B >= 786) begin
                SCH_PWROK <= #`DEL 1;
                ST_PM <= #`DEL S3toS0_clr2;
            end
            else begin
                SCH_PWROK <= #`DEL 0;
            end
        end

        S3toS0_clr2: begin
            PM_SLP_S4_N <= #`DEL 1;
            PM_SCH_RSMRST_N <= #`DEL 1;
            PM_SLP_S3_N <= #`DEL 1;
            PM_RSTWARN <= #`DEL 1;
            IMVP_VR_ON <= #`DEL 1;
            SCH_PWROK <= #`DEL 1;
            RST_CNT12B_N <= #`DEL 0;
            RST_CNT8B_N <= #`DEL 0;
            //CNT12B <= #`DEL 12'b0;
            //CNT8B <= #`DEL 8'b0;
            ST_PM <= #`DEL S3toS0_sec3;
        end

        S3toS0_sec3: begin
            PM_SLP_S4_N <= #`DEL 1;
            PM_SCH_RSMRST_N <= #`DEL 1;
            PM_SLP_S3_N <= #`DEL 1;
            IMVP_VR_ON <= #`DEL 1;
            SCH_PWROK <= #`DEL 1;

            RST_CNT12B_N <= #`DEL 1;
            //CNT12B <= #`DEL CNT12B + 1;
            if (CNT12B >= 2) begin
                PM_RSTWARN <= #`DEL 0;
            end
            else begin
                PM_RSTWARN <= #`DEL 1;
            end

            if (CNT12B >= 3333) begin
                RST_N <= #`DEL 1;
                ST_PM <= #`DEL S0;
            end
            else begin
                RST_N <= #`DEL 0;
            end
        end

        S0: begin
            PM_SLP_S4_N <= #`DEL 1;
            PM_SCH_RSMRST_N <= #`DEL 1;
            PM_SLP_S3_N <= #`DEL 1;
            IMVP_VR_ON <= #`DEL 1;
            SCH_PWROK <= #`DEL 1;
            RST_N <= #`DEL 1;

            RST_CNT8B_N <= #`DEL 0;
            RST_CNT12B_N <= #`DEL 0;
            //CNT8B <= #`DEL 8'b0;
            //CNT12B <= #`DEL 12'b0;

            if (~SLPRDY_N & RSTRDY) begin
                ST_PM <= #`DEL S0toS3;
            end

            if (PM_SYSRST_N) begin
                PM_RSTWARN <= #`DEL 0;
            end
            else begin
                PM_RSTWARN <= #`DEL 1;
            end

            if (SLPRDY_N & SLPMODE & ~RSTRDY) begin
                ST_PM <= #`DEL warmreset;
            end
        end

        S0toS3: begin
            PM_SLP_S4_N <= #`DEL 1;
            PM_SCH_RSMRST_N <= #`DEL 1;

            RST_CNT8B_N <= #`DEL 1;
            //CNT8B <= #`DEL CNT8B + 1;

            if (CNT8B >= 2) begin
                PM_RSTWARN <= #`DEL 1;
            end
            else begin
                PM_RSTWARN <= #`DEL 0;
            end
            
            if (~RSTRDY) begin
                RST_CNT12B_N <= #`DEL 1;
                //CNT12B <= #`DEL CNT12B + 1;
            end

            if (CNT12B >= 3) begin
                RST_N <= #`DEL 0;
            end
            else begin
                RST_N <= #`DEL 1;
            end

            if (CNT12B >= 4) begin
                SCH_PWROK <= #`DEL 0;
            end
            else begin
                SCH_PWROK <= #`DEL 1;
            end

            if (CNT12B >= 5) begin
                IMVP_VR_ON <= #`DEL 0;
            end
            else begin
                IMVP_VR_ON <= #`DEL 1;
            end

            if (CNT12B >= 6) begin
                PM_SLP_S3_N <= #`DEL 0;
            end
            else begin
                PM_SLP_S3_N <= #`DEL 1;
            end

            if (~PM_ALL_SYS_PWRGD) begin
                ST_PM <= #`DEL S3;
            end
        end

        S3: begin
            //PM_RSMRST_PWRGD <= #`DEL 1;
            PM_SLP_S4_N <= #`DEL 1;
            PM_SCH_RSMRST_N <= #`DEL 1;
            PM_SLP_S3_N <= #`DEL 0;
            IMVP_VR_ON <= #`DEL 0;
            SCH_PWROK <= #`DEL 0;
            RST_N <= #`DEL 0;

            if (~SLPMODE) begin
                ST_PM <= #`DEL S4;
            end
            else begin
                if (~SMC_ONOFF_N | SLPRDY_N) begin // wakeup
                    ST_PM <= #`DEL S3toS0_sec1;
                end
            end
        end

        warmreset: begin
            PM_SLP_S4_N <= #`DEL 1;
            PM_SCH_RSMRST_N <= #`DEL 1;
            PM_SLP_S3_N <= #`DEL 1;
            IMVP_VR_ON <= #`DEL 1;
            SCH_PWROK <= #`DEL 1;

            RST_CNT12B_N <= #`DEL 1;

            if (CNT12B > 32) begin
                PM_RSTWARN <= #`DEL 0;
            end
            else begin
                PM_RSTWARN <= #`DEL 1;
            end
            
            if (CNT12B >= 1 & CNT12B <= 39) begin
                RST_N <= #`DEL 0;
            end
            else begin
                RST_N <= #`DEL 1;
            end

            if (CNT12B > 39) begin
                RST_CNT12B_N <= #`DEL 0;
                if (PM_SYSRST_N) begin
                    ST_PM = S0;
                end
            end
        end

        default: begin
          ST_PM <= #`DEL S4;
        end
      endcase
    end
end

always @(posedge SUS_CLK) begin
    if (RST_CNT8B_N) begin
        CNT8B <= #`DEL CNT8B + 1;
    end
    else begin
        CNT8B <= #`DEL 8'b0;
    end

    if (RST_CNT12B_N) begin
        CNT12B <= #`DEL CNT12B + 1;
    end
    else begin
        CNT12B <= #`DEL 12'b0;
    end
end

endmodule

Bookmark: A Website for Xilinx FPGA Study

Posted in HDL on 2007 年 08 月 21 日 by Kun-Yi

http://www.rickysu.com/bo/

一個不錯的心得網站,針對很多Xilinx AppNote. 與設計心得

文章內容包含 VHDL & Verilog

Verilog Using $readmem or $readmemh in Modelsim

Posted in HDL, Verilog on 2006 年 02 月 28 日 by Kun-Yi
在 Model Sim 6.1b裡面 若是要讀一個檔案到記憶體里模擬
可以使用 $readmem or $readmemh
  • $readmem 為一個BIT的格式的讀檔函式
  • $readmemh 則為一個 HEX格式的的讀檔函式
使用方法為 $readmem(“filename",memory);
會讀進filename檔名的檔案,檔案格式則為
@xx YY
@xx 為記憶體定址使用HEX
YY 則為記憶體的內容依據 BIT/HEX 格式配置與實際記憶體大小
Example
memory 為 8BITS且使用 $readmem 則輸入檔案內容如下
@00   1100_0000  0101_1101
@02   0001_1000  1111_0000
使用 $readmemh 則為
@00   C0 5D
@02   18  F0
當為 16BITS 且使用 $readmemh 則輸入檔案內容如下
@00  AA55 CC11
@02  4E67  5A3C

Verilog 設計的注意事項

Posted in HDL on 2006 年 02 月 04 日 by Kun-Yi
今天在寫JTAG 的 TAP 時,嗯應該是昨天了,寫的有點亂,一直在想應該 HDL 不是這樣用的,但是因為沒啥經驗值,也想不出啥好方法.。寫的東西也七零八落地。但剛剛外出走走時,突然想到UML、Embedded System與Software Design的關係。而在用Verilog or VHDL 設計硬體時也是注重抽象化(Abstruct)的觀念。
所以好的設計應該也是將演算法,狀態機等與輸入輸出介面分離最後在設計一個 Middle ware 連結,應該有助釐清設計概念與應用UML等工具。對付複雜性的設計才有可能達成。
可能現在專注力不夠了吧,對於以前上萬行的程式都還能控制與處理。但現在對於超過  500 行左右的程式就有點心有餘而力不足了。常常需要 Refactoring 三四次才能得到一個比較好的結果與想要的效果。
 
TAP 應該分為
State, Input/Output setting, ……等等